1. Technical Field
This invention relates generally to semiconductor devices and fabrication methods therefor, and more particularly, to a semiconductor device having a trench portion in a semiconductor substrate between bit lines and between word lines and a fabrication method therefor.
2. Description of the Related Art
In recent years, non-volatile memory semiconductor devices, in which data is rewritable, have been widely used. In the technical field of such non-volatile memories, developments of downsizing the memory cells are being promoted to obtain higher storage capacity. As non-volatile memories, there has been developed flash memories having Oxide/Nitride/Oxide (ONO) film such as Metal Oxide Nitride Oxide Silicon (MONOS) or Silicon Oxide Nitride Oxide Silicon (SONOS). Among them, for purposes of miniaturizing memory cells, there have been developed flash memories in which the bit lines are embedded in the semiconductor substrate to serve as source/drain regions.
The above-described conventional technique (referred to as conventional technique 1) is described, by reference to FIG. 1 (PRIOR ART) and FIG. 2 (PRIOR ART). FIG. 1 (PRIOR ART) is a top view of a flash memory in accordance with the conventional technique 1. FIG. 2A (PRIOR ART) and FIG. 2B (PRIOR ART) are cross-sectional views thereof. FIG. 2A (PRIOR ART) is a cross-sectional view taken along a line A-A shown in FIG. 1 (PRIOR ART). FIG. 2B (PRIOR ART) is a cross-sectional view taken along a line B-B shown in FIG. 1 (PRIOR ART). Referring to FIG. 1 (PRIOR ART), bit lines 14 run in a vertical direction in FIG. 1 (PRIOR ART), end word lines 15 run in a width direction of the bit lines.
Referring now to FIG. 2A (PRIOR ART) and FIG. 2B (PRIOR ART), the bit lines 14 that serve as source/drain regions are embedded in a semiconductor substrate 10. An ONO film 12 is formed on or above the semiconductor substrate 10. The word lines 15 that serve as gate electrodes are provided on the ONO film 12.
The semiconductor substrate 10, being provided below the word lines (gate electrodes) 15 arranged between the bit tines (between the source/drain regions) 14, serves as a channel. By storing charge in the ONO film 12 on the channel, the flash memory functions as a non-volatile memory.
Japanese Patent Application Publication No. 2004-111874 (hereinafter, referred to as Patent Document 1) and Japanese Patent Application Publication No. 05-198778 (hereinafter, referred to as Patent Document 2) respectively disclose techniques of forming a thermally-oxidized silicon film on the bit lines in a semiconductor device having trench portions between the bit lines 14 and between the word lines 15 in the semiconductor 15 substrate 10. At the time of forming the word lines, trench recess portions are formed in the semiconductor substrate by using the thermally-oxidized silicon film provided on the bit lines as a mask.
In Patent Document 1, there is provided one layer of the word lines in the gate electrode structure above the channel (referred to as conventional technique 2). Meanwhile 1 in Patent Document 2, there are provided a floating gale, a silicon oxide film, and a control gate (word line) in the gate electrode structure above the channel (referred to as conventional technique 3).
FIG. 3A (PRIOR ART) and FIG. 3B (PRIOR ART) are views explaining the problem in the conventional technique 1. FIG. 3A (PRIOR ART) is a top view of a flash memory of the conventional technique 1. FIG. 3A (PRIOR ART) is a cross-sectional view taken along a line B-B shown in FIG. 3A (PRIOR ART). Referring to FIG. 3A (PRIOR ART). according to the conventional technique 1, the charge is written Into the ONO film 12 by 30 applying a high voltage between the bit lines 14 and then trapping in a trap layer, the charge whose energy becomes high in a channel 50 below the word line (gate electrode) 15.
Current in the semiconductor substrate 10 below the word line 15, however, also flows at both sides of the channel 50 below the word line 15, as indicated by dashed arrows shown in FIG. 3A (PRIOR ART). As shown in FIG. 3B (PRIOR ART), the channel expands to the both sides of the channel 50 below the word line 15 (as represented by reference numeral 52). Accordingly, the charge is trapped not only in the ONO film 12 below the word line 15 (as represented by reference numeral 54) but also in the both sides of the word line 15 (as represented by reference numeral 54a).
As stated, when the charge is trapped in the ONO film 12 at both sides of the word line 15, the following problems occur. Firstly, the charge cannot be erased at the time of erase operation. Next, the charge is trapped In the ONO film 12 below adjacent word lines 15. These problems will cause another problem in that the memory cells malfunction. For this reason, it is difficult to narrow the distances between the word lines 15 and downsize the memory cells.
Therefore, it can be considered that the trench portion is provided in the semiconductor substrate 10 between the bit lines 14 and between the word lines 15. However, in the structure (LOCOS structure) having a thermally-oxidized silicon film on the bit lines, the bird beaks are produced and downsizing is difficult. Also, in the conventional technique 3, there is provided an oxide film layer between the control gate and the floating gate, thereby complicating the etch process to form the floating gate, control gate, and trench portion. This is because the oxide film provided on the bit lines is used as an etching mask during the etch process of forming the trench portion.